Many portable electronic devices, such as cameras, cellular telephones, Personal Digital Assistants (PDAs), MP3 players, computers, and other devices include a semiconductor (e.g., complementary metal-oxide-semiconductor; CMOS) imaging device for capturing images. An imaging device includes a focal plane array of pixels, each one of the pixels including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel has a readout circuit that includes an output transistor and a charge storage region connected to the gate of an output transistor. The charge storage region may be constructed as a floating diffusion region. Each pixel includes at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a typical CMOS imaging device, the active elements of a pixel perform the functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region accompanied by charge amplification; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing a reset level and pixel charge. Photon charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by an output transistor.
FIG. 1 illustrates a typical four transistor (4T) pixel 50 utilized in a pixel array of an imaging device, such as a CMOS imaging device. The pixel 50 includes a photosensor 52 (e.g., a photodiode), a storage node N configured as a floating diffusion region, transfer transistor 54, reset transistor 56, charge conversion transistor 58 configured as a source follower transistor, and row select transistor 60. The photosensor 52 is connected to the storage node N by the transfer transistor 54 when the transfer transistor 54 is activated by a transfer control signal TX. The reset transistor 56 is connected between the storage node N and an array pixel supply voltage VAA. A reset control signal RESET is used to activate the reset transistor 56, which resets the storage node N to a known state as is known in the art.
The charge conversion transistor 58 has its gate connected to the storage node N and is connected between the array pixel supply voltage VAA and the row select transistor 60. The charge conversion transistor 58 converts the charge stored at the storage node N into an electrical output signal. The row select transistor 60 is controllable by a row select signal ROW for selectively outputting the output signal OUT from the charge conversion transistor 58. For each pixel 50, two output signals are conventionally generated, one being a reset signal Vrst generated after the storage node N is reset, the other being an image or photo signal Vsig generated after charges are transferred from the photosensor 52 to the storage node N.
FIG. 2 shows an imaging device 200 that includes an array 230 of pixels (such as the pixel 50 illustrated in FIG. 1) and a timing and control circuit 232. The timing and control circuit 232 provides timing and control signals for enabling the reading out of signals from pixels of the pixel array 230 in a manner commonly known to those skilled in the art. The pixel array 230 has dimensions of M rows by N columns of pixels, with the size of the pixel array 230 depending on a particular application.
Signals from the imaging device 200 are typically read out a row at a time using a column parallel readout architecture. The timing and control circuit 232 selects a particular row of pixels in the pixel array 230 by controlling the operation of a row addressing circuit 234 and row drivers 240. Signals stored in the selected row of pixels are provided to a readout circuit 242 in the manner described above. The signals are read twice from each of the columns and then read out sequentially or in parallel using a column addressing circuit 244. The pixel signals (Vrst, Vsig) corresponding to the reset pixel signal and image pixel signal are provided as outputs of the readout circuit 242, and are typically subtracted by a differential amplifier 260 in a correlated double sampling operation and the result digitized by an analog to digital converter to provide a digital pixel signal. The digital pixel signals represent an image captured by pixel array 230 and then are processed in an image processing circuit 268 to provide an output image.
Many of the portable electronic devices that include a CMOS imaging device, e.g., cameras, cell phones, PDA, etc., are designed for operation in different levels of light. For example, a camera may include a first setting for use under low ambient light conditions and another setting for use under high ambient light conditions. Including circuitry in a CMOS imaging device for providing different levels of gain for handling different ambient light conditions increases the costs and materials required to manufacture the device.